1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a link program circuit for programming an internal state of a core circuit with link elements. More particularly, the invention relates to an arrangement of programmable link elements in the semiconductor integrated circuit device.
2. Description of the Background Art
In a semiconductor integrated circuit device, a fuse program circuit (link circuit) is arranged for adjusting internal operation characteristics after manufacturing of the circuit device. By programming (blowing or no-blowing) fuse elements (link elements) in this fuse program circuit, variations in manufacturing parameters are compensated for to set the internal circuit characteristics optimum values, and further a defective bit in a storage device is repaired so that the manufacturing yield is improved. The fuse program circuit is generally referred to as an LT (Laser Trimming) link circuit because laser is generally used for programming the link elements (fuse elements).
A redundant circuit for repairing a defective bit is an example of the circuitry utilizing the LT link circuit, as is disclosed in Japanese Patent Laying-Open No. 11-31398. The defective bit repair circuit repairs a defective bit by programming a defective address with the link element to replace the circuit at the defective address with a redundant circuit. This LT link circuit is arranged for each fault repairing unit such as a row block.
The LT link circuit is used for adjusting the delay time of a delay circuit to optimize the operation timings of internal circuitry. In this case, the number of delay stages or the operation current is adjusted by programming the link elements, to adjust the timing of signals, resulting in an improved operation margin.
The semiconductor integrated circuit device produces an internal voltage for a specific internal operation from an external power supply voltage. Such internal voltages include a reference voltage defining an operation power supply current, and a reference voltage for determining the voltage level of an internal power supply voltage or an internal high voltage. When the voltage level of the reference voltage changes from a predetermined voltage level, internal operation conditions change so that intended operation characteristics cannot be achieved. For adjusting the voltage level of the reference voltage, the LT link circuit is arranged for such a circuit for generating the reference voltage.
As described above, the purpose of provision of the LT link circuit is not restricted to repairing of defective bits in the semiconductor memory device. LT link circuits are generally arranged in the semiconductor integrated circuit devices for compensating for variations in various operation conditions caused by variations in manufacturing parameters. The LT link circuit is generally arranged near a target circuit. This arrangement is employed for preventing complication of signal interconnection lines. Also, this arrangement is employed in the case of repairing defective bits, because a signal indicating use or nonuse of a redundant bit must be transmitted fast for fast repairing of the defective bits.
FIG. 57 shows an example of a structure of the conventional LT link circuit. In FIG. 57, an LT link circuit 1 includes: a P-channel MOS transistor (insulated gate field effect transistor) 1a which is connected between a power supply node NDP and an internal node ND0, and receives on its gate a reset signal RST_B; and a link element 1c and an N-channel MOS transistor 1b, which are connected in series between internal node ND0 and a ground node. N-channel MOS transistor 1b receives reset signal RST_B on its gate.
LT link circuit 1 further includes: an inverter 1d which inverts a signal on internal node ND0, and outputs program data FDATA; and a P-channel MOS transistor 1e which receives program data FDATA received from inverter 1d on a gate thereof, and selectively couples power supply node NDP to internal node ND0 electrically. Inverter 1d and MOS transistor 1e form a so-called half latch.
When reset signal RST_B is at L-level, MOS transistor 1b is off, and MOS transistor 1a is on, so that MOS transistor 1a charges internal node ND0 to the power supply voltage level. Accordingly, inverter 1d drives program data FDATA to the L-level so that P-channel MOS transistor 1e is turned on, and inverter 1d and MOS transistor 1e latch program data FDATA.
When reset signal RST_B attains H-level, MOS transistor 1a is turned off, and MOS transistor 1b is turned on. When link element (fuse element) 1c is blown off, internal node ND0 maintains H-level, and program data FDATA attains L-level. If link element 1c is not blown, a path for current flowing from internal node ND0 to the ground node is present, and internal node ND0 attains L-level, and thereby program data FDATA generated from inverter 1d attains H-level. In this state, MOS transistor 1e is off.
Accordingly, when reset signal RST_B attains H-level, program data FDATA is set to a logical level corresponding to blowing/non-blowing of link element 1c. This program data FDATA is applied to a target circuit or a circuit of interest in the succeeding stage for achieving an intended internal circuit operation.
FIG. 58 shows, by way of example, a structure of a circuit using the LT (laser trimming) information. In FIG. 58, a reference voltage generating circuit for generating a reference voltage Vref is shown as an example of an internal circuit. In FIG. 58, the reference voltage generating circuit includes: a constant current source CRS connected between a power supply node NDP1 and an output node ND1; resistance elements R0-Rn connected in series between output node ND1 and the ground node; and N-channel MOS transistors TR1-TRn connected in parallel to resistance elements R1-Rn to receive program data FDATA1-FDATAn on their gates, respectively.
In the reference voltage generating circuit shown in FIG. 58, the voltage level of reference voltage Vref depends on a resistance value between output node ND1 and the ground node as well as a current I flowing from constant current source CRS. By selectively setting program data FDATA1-FDATAn to H-level or L-level by the LT link circuit, MOS transistors TR1-TRn are selectively turned on/off so that the resistance value between node ND1 and the ground node is adjusted. When all MOS transistors TR1-TRn are made conductive, resistance elements each R1-Rn attain a short-circuited state, and a state is achieved equivalently that only resistance element R0 is connected between output node ND1 and the ground node. In this state, reference voltage Vref is at the voltage level expressed by Ixc2x7R0, where R0 represents a resistance value of resistance element R0.
When all MOS transistors TR0-TRn are off, the resistance value between output node ND1 and the ground node becomes equal to (R0+. . . +Rn), and reference voltage Vref is at the voltage level expressed by Ixc2x7R, where R represents a combined resistance of series-connected resistance elements R0-Rn.
Therefore, by selectively turning on/off these MOS transistors TR1-TRn in accordance with program data FDATA1-FDATAn, the voltage level of reference voltage Vref can be adjusted to the optimum level, and can be adjusted so as to optimize the internal operation.
FIG. 59 schematically shows a whole structure of a semiconductor memory device as an example of the semiconductor integrated circuit device. The semiconductor memory device shown in FIG. 59 is an eRAM (embedded Dynamic Random Access Memory), which is integrated with a logic such as a processor on a common semiconductor chip.
In FIG. 59, the semiconductor memory device includes: memory cell arrays 2a and 2b each having a plurality of memory cells arranged in rows and columns; a row control portion 3 arranged between memory cell arrays 2a and 2b for performing operations related to row selection in memory cells 2a and 2b; data path portions 4a and 4b for transmitting data between the selected memory cells in memory cell arrays 2a and 2b and an external device such as a logic; a control portion 5 for controlling the operation of this semiconductor memory device in accordance with external control signals; and a power supply circuit portion 6 for producing an internal voltage required in the semiconductor memory device.
Row control portion 3 includes row decoders for selecting the memory cell rows in memory cell arrays 2a and 2b, a sense amplifier control circuit for controlling sense amplifier circuits that sense, amplify and latch the data of selected memory cells, and redundant row decoders for repairing a defective memory cell row. For adjusting the activation timing of the sense amplifier circuit, and for programming a defective row address, row control portion 3 is provided with LT link circuits 1 arranged near target circuits, respectively.
Each of data path portions 4a and 4b includes a write driver and a preamplifier arranged corresponding to each of memory cell arrays 2a and 2b for writing and reading data, a defective column repairing circuit for repairing a defective column, and a data input/output circuit forming an external interface. In each of data path portions 4a and 4b, the defective column repairing circuit usually repairs a defective column on a basis of an internal data line. Therefore, a redundant I/O line (spare I/O line) is arranged for a predetermined number of internal data lines (I/O lines). The defective column address program circuit is arranged for each of these redundant I/O lines. For programming a defective column address, LT link circuits 1 are likewise arranged in data path portions 4a and 4b. 
Control portion 5 operates in accordance with the externally applied control signal and the address signal to produce signals for selecting a memory cell row in the semiconductor memory device, for selecting the memory cell column and for controlling write/read of data. In this control portion 5, LT link circuitry 1 is arranged for adjusting the generation timing of the internal control signal.
Power supply circuit portion 6 includes an internal voltage down converter for producing an internal power supply voltage from the external power supply voltage, a high-voltage generating circuit for generating a high voltage (boosted voltage) to be transmitted onto a selected word line, and a substrate bias generating circuit for generating a substrate bias voltage to be applied to a substrate region of the memory cell array. The voltage level of the internal power supply voltage to be produced depends on the reference voltage generated from the reference voltage generating circuit. For adjusting the voltage level of this reference voltage, LT link circuits 1 are arranged. For adjusting the current drive capability of the internal voltage down converter, which generates the internal power supply voltage, unit current drive transistors are selectively turned on, and LT link circuits 1 are utilized for this turn-on.
When generating a high voltage or a substrate voltage, the device utilizes a charge pump circuit, which performs a charge pump operation in response to a dock signal. In this case, LT link circuit 1 is utilized for adjusting a cycle period of the clock signal and/or the charge pump capability.
These LT link circuits are arranged as dose as possible to the target circuits for reducing the interconnection line lengths. As shown in FIG. 59, therefore, LT link circuits 1 are distributed substantially over an entire of the semiconductor memory device. LT link circuit 1 includes link element 1c, as shown in FIG. 57. An occupation area of link element 1c is larger than a layout area of a usual MOS transistor, resulting in a problem that the LT link circuits occupy a large area on the chip.
A laser or energy beam is used for programming a link element in LT link circuit 1. Since this laser beam is emitted from a portion outside the chip, another interconnection line cannot be disposed above this link element. This disadvantageously lowers the flexibility in interconnection layout. Particularly, in the case of eRAM, data bits to be input/output are greater in number so that it is extremely difficult to arrange LT link circuits 1 between the internal data lines in data path portions 4a and 4b particularly.
Although the eRAM is integrated with a logic such as a processor on a common semiconductor chip, other circuit blocks such as SRAM (Static Random Access Memory), a nonvolatile memory and an analog core for processing an analog signal are also integrated on the same semiconductor chip. Therefore, interconnection lines extending over the eRAM could not utilized as interconnection lines connecting the logic to the circuits blocks other than the eRAM, because the trimming must be effected on the LT link circuits arranged distributedly in the eRAM. Accordingly, the interconnection for the circuit blocks other than the eRAM must be made avoiding an area of the eRAM, resulting in disadvantageous increase in interconnection area and therefore chip area of the semiconductor integrated circuit device.
In LT link circuit 1, it is impossible to change program contents after the link elements are programmed with an energy beam such as the laser. Therefore, a program fault cannot be repaired if the program fault occurs in programming of many LT link circuits, which lowers the manufacturing yield. In particular, if many LT link circuits 1 are distributed on the semiconductor chip, many steps are required for programming all the LT link circuits so that the programming of the LT circuits takes a long time. Further, it would be difficult to program all the LT link circuits accurately, and the program defective is liable to occur. Once the signal timing or the like is set by the programming of the link elements, the re-adjustment thereof is impossible thereafter.
Each LT link circuit 1 is disposed near the target circuit, and the output signal (program data FDATA) thereof is applied only to the target circuit. This program information cannot be externally read out from the integrated circuit device. Therefore, it is impossible to detect whether each LT link circuit is accurately programmed or not.
Since the LT link circuit is programmed by the energy beam such as a laser beam in a destructive manner, it is impossible to change the program information in the semiconductor integrated circuit device after it is packaged.
An object of the invention is to provide a semiconductor integrated circuit device, in which restrictions on a layout of interconnection lines can be reduced without increasing an area occupied by the interconnection lines.
Another object of the invention is to provide a semiconductor integrated circuit device, in which restrictions on arrangement positions of LT link circuits are reduced, and flexibility in circuit layout is improved.
Still another object of the invention is to provide a semiconductor integrated circuit device, which allows reprogramming of LT information.
Yet another object of the invention is to provide a semiconductor integrated circuit device, which allows external monitoring of LT information.
Further another object of the invention is to provide a semiconductor integrated circuit device, which can improve yield of programming of LT information.
A further object of the invention is to provide a semiconductor integrated circuit device, which allows efficient programming of LT information.
A semiconductor integrated circuit device according to the present invention includes: at least one core circuit for performing a predetermined operation; an LT link circuitry arranged outside the core circuit for holding programmable internal information for setting an internal state of the core circuit; a transfer circuit for serially transferring the information held by the LT link circuitry to the core circuit upon power-up; a plurality of latch circuits disposed in the core circuit and arranged corresponding to predetermined internal circuits for latching corresponding internal information and applying the latched information to the corresponding predetermined internal circuit portions, respectively; and a transfer control circuit arranged in the core circuit for converting serial information transferred from the transfer circuit to parallel information, and transferring the parallel information to the plurality of latch circuits.
The LT link circuitry is arranged outside the core circuit, and the internal information held by the LT link circuitry is transferred to the latch circuits arranged corresponding to the internal circuits in the core circuit. Therefore, the link element is not disposed in the core circuit so that the interconnection layout area can be significantly reduced. The link element is not disposed in the core circuit, but merely the latch circuit is disposed therein, reducing an area penalty of the link elements. Arrangement of the LT link circuitry outside the core circuit significantly improves the flexibility in arrangement position of the LT link circuits so that the core circuit can be designed in an optimum manner to reduce the occupying area in the chip.